Upon losing the process node battle to the foundry leader TSMC, IDMs like Intel, AMD and others are after Chiplet. Does it sound unfair? Or, is Chiplet a new technology core with the latent potential to grow and unleash Creative Destruction to the monolithic chip fabrication supremacy of TSMC? In the discourse of how IDMs like Intel can survive or regain the lost glory with older process node competence, the Chiplet technology core has been surfacing. Some experts think that the disaggregation strategy of Chiplet technology will likely emerge as a better alternative to monolithic design. Hence, companies like Intel, having a solid foothold in Chiplet technology, may unleash a creative wave of destruction to TSMC’s process node supremacy. Or, is it the acceptance of IDMs that they will never win over TSMC in process node competence? Hence, they offer an inferior alternative for having complex chips by mixing Chiplets.
Historical creative destruction lessons
Irrespective of the greatness, all technology cores slow down and reach saturation. To overcome the limitation of further growth, innovators pursue Reinvention. They change matured technology core with emerging one. Invariably, reinvention waves out of emerging technology core debut as inferior alternatives. But some of them succeed by unfolding latent potential as a creative wave of destruction.
For example, the digital camera in the 1980s was inferior to the film camera. But it kept growing as a creative wave of destruction, creating the Kodak moment. Similarly, LED light bulb started the journey in an inferior form but succeeded as a creative destruction force. There have been many examples, from mobile phones and personal computers to LCD television.
In retrospect, all major products and industries have been evolving through incremental advancement and reinvention in an episodic form. Surprisingly, all reinvention waves began the journey in primitive form. But some of them succeeded as creative destruction forces. Hence, the semiconductor industry will also experience a similar transformation to overcome the growing limitation. But which technology core will likely succeed in fueling creative destruction force?
Moore’s law faces complexity, cost, and physical limits
After the invention of the integrated circuit in 1961, the advancement of process technology and the urgency of placing an increasing number of transistors on the same die, the chip density started rising. In 1965, Gordon Moore predicted that the number of transistors in a single chip would keep doubling roughly every two years.
To increase chip density, we need to reduce the dimension of the Transistor and bring them closer. Hence, we must advance the transistor design and improve the silicon process technology. One of the critical building blocks is that lithography technology determines how small features we can project on the wafer. Due to the advancement of using light sources of smaller wavelengths, lithography machine makers succeeded in reducing the feature dimension. Besides, other process equipment, chemicals, and gases kept improving to keep pace with the advancement of the photolithography machine. As progress to the next node in packing more transistors on the same chip area kept improving performance, reducing energy footprint, and reducing cost per transistor, equipment makers kept asking for chips with growing density. Hence, transistor density kept doubling roughly over two years—keeping Moore’s law alive.
On the cost front, plant capital expenditure has been exponentially growing. For example, for a 5nm plant, semiconductor firms need as high as $15 billion, 25% higher than the immediate higher 7nm plant. And for the 3-nm plant, capital expenditure shoots up to $18 billion. Besides, learning complexity and proprietary competence for yield optimization have also been accelerating. For example, despite having money and access to technology, Intel has been struggling for years to migrate from 10nm to 7nm process node. Besides, lead users to cooperate in process and design optimization and place high volume orders to get their chips processed with the next node.
Moore’s Law faces physical limits
Over the decades, lithography machine makers kept targeting light sources having a smaller wavelength, reaching 13.5 nm extreme ultraviolet (EUV). To overcome the extreme complexity of producing and handling EUV light, ASML and its partners had to perform R&D over two decades to release their EUV machine in 2019. EUV light is extremely difficult to create, and even lenses absorb it. In making EUV light source for developing lithography machines for sub 10nm feature dimension, scientists and engineers reached the physical limit of optics and mechatronics. Furthermore, the feature dimension has reached the atomic level. For example, 5nm is the size of 10 large atoms.
Moving to a smaller wavelength light source is not an option. Although higher numerical aperture (NA) offers some legroom, the cost of lithography machines and other fab equipment rises exponentially. For example, instead of $200 million for 5nm, foundries will be required to pay $450 million for each unit of ASML’s EUV photolithography machine for a 2nm process node. Besides, such cost escalation will also demand higher Economies of Scale and organizational competence. Hence, the industry faces the limit of doubling the chip density over 24 months.
The growing complexity, cost, and scale of Moore’s law has led to monopolization—winner takes all
Moving to the next node to produce higher-density chips demands a more complex and expensive machine. As a result, plant cost, economies of scale, and competence for yield optimization kept rising. Consequentially, the number of firms producing high-end chips kept falling. For example, the number of semiconductor firms producing chips using the latest node fell from over 30 in 2000 to two in 2020. And in 2022, TSMC seems to be the sole monopoly in building the chips at the most advanced node—3nm.
Birth of Chiplet technology
To overcome the physical limit, cost, scale, and competence of meeting Moore’s law, IDMs like Intel has been touting in favor of Chiplet. The argument has been that a large chip, known as a system on chip or SoC, could be divided into pieces. Instead of fabricating an SoC on a single die, pieces could be fabricated separately on individual dies. Furthermore, all modules of an SoC do not require the latest process node to fabricate. Hence, older process nodes could produce some tiles, while the most critical ones may need the latest node. Later on, each of them could be connected by placing them one after another, whether horizontally or vertically, to get the final SoC.
One of the goals is to reduce product development time and costs by integrating pre-developed tiles in an IC package. From a menu of modular dies, or chiplets, chip makers can mix and match the chiplets and connect them using a die-to-die interconnect scheme. Hence, instead of shrinking different functions of SoCs at each node and packing them onto a monolithic die, Chiplet offers modularizing that approach.
By the way, this isn’t a new concept. Several companies have a track record of shipping chiplet-like designs. They have to do it as they cannot move to the next process nodes for packaging a growing number of transistors on the same chip. But upon facing the problem of coping with the complexity of moving to the next node every 18 to 24 months, IDMs have been trying to create a snowball effect. But there has been an argument that modularization may have a lower cost and better yield than a monolithic die. Hence, Chiplet may turn out as a better approach to chip design, leading to superior performance. By the way, IBM was already building systems that included the chiplet concept as early as 1964.
Open standard for creating a market for tiles
Several prominent IDMs have been aggressively demonstrating their Chiplet technology portfolio. They have also been leading the process of addressing compatibility issues, leading to open standards. In this regard, the recent introduction of the Universal Chiplet Interconnect Express (UCIe) Specification 1.0 is an enabling technology. Among others, this new UCIe Chiplet standard is supported by Intel, AMD, Arm, TSMC, and Samsung, among others, support UCIe. Basically, this is an extension of the Peripheral Component Interconnect Express (PCIe), a standardized interface for PCBs (printed circuit boards). Hence, Chiplet promoters are after taking PCBs’ approach of mixing and matching various devices produced by different vendors for functions such as graphics, memory, and storage inside the package. UCIe brings PCIe down to the level of die-to-die interconnects, giving birth to Chiplet technology. And industry heavyweights such as AMD, Arm, ASE, Google, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC are after it.
Intel’s Titles
At the Hot Chips 2022 conference, Intel promoted the idea of fusing multiple tiny tiles for its upcoming 14th-generation ‘Meteor Lake’ and ‘Arrow Lake’ processor families. It’s an Intel solution to get out of the race to attain the latest process nodes like 5nm, 3nm, or 2nm. For Intel, little tiles are a big deal to break free of the limits of monolithic chip design. From the details, it appears that this is Intel’s significant departure from a monolithic structure, as it struggles to keep moving to sub-10 nm nodes. Intel argues that it will lead to faster—and, maybe, more affordable—processors in the years to come.
In citing the possible superiority of Intel’s Chiplet strategy, experts refer to the three most important limitations of monolithic chip design and production. It begins with yield. The next one is that graphics processors and CPUs tend to function better when each is made under its optimal process technology. But the monolithic approach of designing all components on a single chip force to use of the same manufacturing process for all the building blocks, negatively affecting performance. The last one is easy changes. It is not simple to make changes to just one component—say, the memory controller or the video processor– when everything’s baked together. Hence, by adopting a chiplet design approach, Intel will mitigate these and other issues.
Intel’s Foveros technology
To mix and match compute tiles, Intel has developed Foveros technology for wafer-level packaging capabilities to provide a 3D stacking solution. This packaging technology enables Intel to build processors with tiles stacked vertically rather than side-by-side. Intel uses Foveros to combine 47 tiles with more than 100 billion transistors to make its enormous “ Ponte Vecchio” chip. These chiplets are produced using five manufacturing process nodes across Intel and TSMC. Intel plans to use that same interconnect technology in its upcoming Meteor Lake and Arrow Lake processors.
AMD Chiplet
AMD has been using chiplet designs for its Ryzen processors for some time. AMD’s chiplets debuted in the chip market in 2015. There are claims that AMD redesigned its large, complex, and powerful flagship server chips for greater efficiencies using the Chiplet technology. Instead of being built on a single die and engineered from scratch, AMD designs the chip as multiple smaller pieces – or chiplets – that are then “stitched” together. By breaking up a chip into smaller pieces, AMD reduced manufacturing costs by 40%. Furthermore, it gives AMD the option of reusing two server chiplets and designing something less costly that works for desktops.
TSMC in Chiplet
Despite being the top performer in monolithic chip fabrication using the latest process technology node, TSMC recognizes the importance of Chiplets. Although most high-end processors are currently monolithic, design methodologies are slowly shifting to multi-chiplet modules. Instead of making the whole chip using increasingly expensive leading-edge fabrication technologies, only a selective portion will be made using it. As a result, multi-chiplet system-in-packages (SiPs) are expected to become much more widespread. Hence, TSMC established its 3DFabric Alliance in Oct 2022. In leading theAlliance, TSMC will set specific ground rules and standards. To unify the design ecosystem with qualified EDA tools and flows, TSMC has already developed its 3Dblox standard. It covers various aspects of building multi-chiplet devices featuring 2.5D and 3D packaging methodologies; some of them are physical implementation, power consumption, heat dissipation, electro-migration IR drop (EMIR), and timing/physical verification.
In the coming years, SiPs are expected to become much more widespread. Understandably, large companies like AMD and Nvidia tend to develop their IP, interconnection, and packaging technologies. 3DFabric Alliance for multi-chiplet SiPs promises to make the development of complex, chiplet-style processors accessible to smaller companies. Hence, the TSMC-led alliance will enable fabless companies to design and produce large chips, likely taking away the market shares of IDMs.
Is Chiplet winning, survival, or death strategy of IDMs?
The chiplet approach of fabricating a large chip by assembling multiple smaller ones is not new. It has been around since the 1960s. But due to the rapid growth of processing technology doubling the number of transistors on the same chip, it kept losing its appeal. But it has gained new attention as IDMs have been failing to cope with the complexity and cost of the next node. Notably, they have fallen behind TSMC.
Of course, the Chiplet approach of modular design and fabrication has merit for the optimum use of different process nodes. But is this approach of fabricating large chips a survival or winning strategy of IDMs? Will this approach weaken the appeal of the next node of process technology in making smaller transistors? Particularly, through Chiplet technology, will IDMs regain their edge and take over TSMC’s supremacy?
Chiplet technology is not a substitute for the next process node. Hence, by adopting it, IDMs cannot erode the market value of TSMC’s competence in making chips with next-generation technology. Instead, IDMs will keep increasing their dependence on TSMC to get the most valuable tile produced by the latest node. Hence, as IDMs join fabless companies, the customer base of TSMC will expand. On the other hand, TSMC’s monopoly status in the latest process node will remain uncontested.
Due to the growing popularity of Chiplet, creating an open market of tiles, IDMs will likely be suffering from the diffusion of their core competence. Fabless companies will face a decreasing barrier to designing chips using tiles to penetrate the large chip market. On the other hand, OSAT companies will gain more substantial relevance and customer base for assembling multiple tiles in the same package. Does it mean that upon losing the battle to TSMC in moving to the next node, IDMs make them more vulnerable by adopting Chiplet approach as the mainstay?
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